Lattice ispMach 4128/4256
Softgun simulates the JTAG interface of the Lattice ispMach4128/4256.
The chips can be programmed according to IEEE-1532. The programable logic of the chip is not simulated.
The interface of a instance of a chip with the name "mach4128" consists of the
following logical signal nodes:
Configuration File Options
In the configuration file the variant of the Chip is selected. The variants
"LC4128V_XXT100" and "LC4256V_XXT100" are available. The disk image with the contents of the CPLD is generated in the image directory configured in the global section
- Erase/Program/Read. The result is stored as binary in a file.
- Usercode programing. The Usercode is stored in the last four bytes of the file.
- Prints warnings when timing constraints are violated. Unfortunately the Lattice tool "ispMachVME" generates faster timings than documented in the boundary description files provided by Lattice, so the values generated by ispMachVME are used for timing checks. This safes me from beeing drowned by error messages.
- Minimum Idle clock cycle check is NOT implemented currently.