NS9750 I2C Master/Slave Emulation

The Netsilicon NS9750/NS9360 has a builtin I2C Master and a Slave. Multiple masters can be on the I2C bus. The I2C Slave can be used independently at the same time even if it is integrated in the same modules.

Device bugs

The NS9750 I2C master does not keep the minimal time between a I2C stop condition and the next start condition if the stop condition is generated by one master and the start condition by another master. This time is called "TBUF" in the I2C specification. This bug can lead to corrupted data because one device might not detect the stop condition and the other device does not detect a start condition. The workaround for this bug is to increase the spike filter so that T_BUF is long enough. Unfortunately this reduces the possible speed of the Bus.
The NS9750 I2C master does not release the SCL line on Arbitration loss. The I2C master requires a reset after this condition. Unfortunately there is only one reset bit for master and slave. So this reset also resets the slave. Any data in the buffers of the slave are lost.

Emulator bugs / Missing features

The spike filter width has no effect on the timing except on TBUF.
The emulator has the TBUF and arbitration loss bug intentionally