ENC28J60 Ethernet Controller

The ENC28J60 is a 10 MBit Ethernet controller with integrated PHY. Because it has a SPI Interface it is used often with very small Microcontrollers. It has 8kB of internal SRAM. It can calculate the TCP/IP-Header checksums. Softgun simulates the ENC28J60 on logical Signal level. An Instance of the ENC28J60 has the following 5 signals:

enc28j60.sck	# SPI clock line
enc28j60.mosi	# SPI data in line
enc28j60.miso	# SPI data out line
enc28j60.ncs	# negated chip select
enc28j60.irq	# Interrupt request

Supported features

MAC filters
DMA (memory copy in internal buffer)
TCP checksuming
Ethernet CRC calculation
Configurable paket dropping useful for testing error recovery of TCP Implementations

Untested features

MAC Hash table filter
Pattern match filter
Transmit status Vector

Example configuration section

[enc28j60]
host_ifname: simu0 
host_ip: 192.168.80.3
rxdrop: 5 # Throws away 5 percent of received packets
txdrop: 5 # Throws away 5 percent of transmitted packets